1. Field of the Invention
The present invention relates to a semiconductor integrated circuit in which the level of a node of the circuit during the standby mode is not uniquely determined and the sub-threshold leaking current across the node is reduced by taking the countermeasures so as to reduce the standby power consumption.
2. Description of the Related Art
It is known that complementary metal-oxide semiconductor (CMOS) circuits, such as the semiconductor integrated circuit, exhibit extremely low standby power.
For the sake of simplicity of description, suppose a simple CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor. In such CMOS circuit, when the input signal is set to the high level, the p-channel transistor is set in OFF state and the n-channel transistor is set in ON state. After the discharging of a capacitive load at the output of the CMOS circuit is performed, the n-channel transistor is set in OFF state. Normally, in this condition, the power consumption of the CMOS circuit is negligible.
When the input signal is set to the low level, the p-channel transistor is set in ON state and the n-channel transistor is set in OFF state. After the discharging of the capacitive load at the output of the CMOS circuit is performed, the p-channel transistor is set in OFF state. Normally, in this condition, the power consumption of the CMOS circuit is also negligible.
However, the level of integration of semiconductor integrated circuits is further increased from that of the conventional version with the recent developments of micro-fabrication technology used in CMOS circuits. When compared to a MOS transistor with the channel length of 1 xcexcm, a MOS transistor with the channel length of 0.1 xcexcm has a lower threshold voltage, and the drain current is not zero if the gate voltage (or the gate-to-source voltage) is less than the threshold voltage. Hereinafter, the drain current which leaks from the MOS transistor in the region in which the gate voltage is less than the threshold voltage is called the sub-threshold leaking current, and the region in which the gate voltage is less than the threshold voltage is called the sub-threshold region. This sub-threshold leaking current exponentially increases to the gate voltage.
Hence, the increase of the sub-threshold leaking current described above is detrimental to the demand for providing a semiconductor integrated circuit that exhibits low power consumption. Specifically, the power consumption of a semiconductor integrated circuit, including MOS transistors produced by the micro-fabrication method, during the standby mode depends on the amount of the sub-threshold leaking current. In order to reduce the power consumption, it is necessary to reduce the sub-threshold leaking current.
On the other hand, an improved semiconductor integrated circuit has been proposed, and, in this circuit, the sub-threshold leaking current is reduced by taking the countermeasures so as to reduce the standby power consumption. This semiconductor integrated circuit includes an internal circuit having MOS transistors produced by the micro-fabrication method. To prevent the lowering of the breakdown voltage of such MOS transistors, a voltage lowering circuit is provided to generate a lowered power-source voltage from an external power-source voltage. The voltage lowering circuit supplies the lowered power-source voltage to the MOS transistors of the internal circuit, thereby reducing the sub-threshold leaking current.
FIG. 1 shows a semiconductor integrated circuit in which a conventional method for reducing the sub-threshold leaking current is incorporated. Regarding the conventional method in FIG. 1, Japanese Laid-Open Patent Application No. 5-210976 discloses a similar method to reduce the sub-threshold leaking current.
As shown in FIG. 1, the semiconductor integrated circuit includes a logic circuit 100, a switching device 101, a switching device 102, and a target circuit 107. In the present example, the target circuit 107 is the circuit to which the countermeasure against the sub-threshold leaking current is to be taken.
In FIG. 1, xe2x80x9cViizxe2x80x9d and xe2x80x9cVssxxe2x80x9d indicate the power-source lines which deliver the power-source voltages to reduce the sub-threshold leaking current, and xe2x80x9cViixe2x80x9d and xe2x80x9cVssxe2x80x9d indicate the power-source lines which deliver the power-source voltages. When the semiconductor integrated circuit of FIG. 1 is set in the active mode, the voltage of the power-source line xe2x80x9cViizxe2x80x9d is the same as the voltage of the power-source line xe2x80x9cViixe2x80x9d. When the semiconductor integrated circuit of FIG. 1 is set in the standby mode, the voltage of the power-source line xe2x80x9cViizxe2x80x9d is set in a floating state. Hereinafter, the xe2x80x9cViizxe2x80x9d and xe2x80x9cVssxxe2x80x9d are called the countermeasure voltage lines, and the power-source voltage lines xe2x80x9cViixe2x80x9d and xe2x80x9cVssxe2x80x9d are called the normal voltage lines, for the sake of convenience of description.
In the semiconductor integrated circuit of FIG. 1, the switching device 101 connects the countermeasure voltage line Viiz with the normal voltage line Vii. The switching device 102 connects the countermeasure voltage line Vssx with the normal voltage line Vss. The logic circuit 100 receives input signals and performs a logic operation for the input signals. A standby mode signal xe2x80x9cstbxxe2x80x9d indicates whether the integrated circuit is set in the standby mode, and this standby mode signal is input to the logic circuit 100. In response to the standby node signal xe2x80x9cstbxxe2x80x9d, the logic circuit 100 respectively outputs signals xe2x80x9cn101xe2x80x9d and xe2x80x9cn102xe2x80x9d to the switching devices 101 and 102 through the logic operation. Namely, when the integrated circuit is set in the standby mode, the switching devices 101 and 102 are set in OFF state by the output signals xe2x80x9cn101xe2x80x9d and xe2x80x9cn102xe2x80x9d of the logic circuit 100. When the integrated circuit is set in the active mode, the switching devices 101 and 102 are set in ON state by the output signals xe2x80x9cn101xe2x80x9d and xe2x80x9cn102xe2x80x9d of the logic circuit 100.
In the semiconductor integrated circuit of FIG. 1, the switching devices 101 and 102 are constructed by using high-threshold transistors. The switching devices 101 and 102 serve to provide the countermeasure power-source voltages of the voltage lines xe2x80x9cViizxe2x80x9d and xe2x80x9cVssxxe2x80x9d from the normal power-source voltages of the voltage lines xe2x80x9cViixe2x80x9d and xe2x80x9cVssxe2x80x9d. Because of the high-threshold structure of the transistors 101 and 102, the sub-threshold leaking current across each of the transistors 101 and 102 during the standby mode is virtually negligible.
In the semiconductor integrated circuit of FIG. 1, the target circuit 107 is comprised of two simple inverters that are concatenated, the first inverter including a p-channel MOS transistor 103 and an n-channel MOS transistor 104, and the second inverter including a p-channel MOS transistor 105 and an n-channel MOS transistor 106. An input signal xe2x80x9cn103xe2x80x9d, the level of which is uniquely determined during the standby mode, is supplied to the inputs of the transistors 103 and 104 of the target circuit 107.
Suppose that the input signal xe2x80x9cn103xe2x80x9d is set at the low level when the integrated circuit is set in the standby mode. When the input signal xe2x80x9cn103xe2x80x9d is at the low level, the transistor 103 is set in ON state, and the transistor 104 is set in OFF state. In this condition, the sub-threshold leaking current may occur at the transistor 104. To avoid this, the countermeasure is taken such that the source of the transistor 103 is connected to the normal voltage line xe2x80x9cViixe2x80x9d and the source of the transistor 104 is connected to the countermeasure voltage line xe2x80x9cVssxxe2x80x9d. During the standby mode, the switching device 102 is set in OFF state, the source of the transistor 104 is disconnected from the normal voltage line xe2x80x9cVssxe2x80x9d due to the OFF state of the switching device 102, and the sub-threshold leaking current which tends to flow through the source/drain path of the transistor 104 is avoided by the connection of the source of the transistor 104 and the countermeasure voltage line xe2x80x9cVssxxe2x80x9d.
Further, the input signal supplied to the second inverter of the target circuit 107 is set at the high level. The transistor 105 is set in OFF state, and the transistor 106 is set in ON state. In this condition, the sub-threshold leaking current may occur at the transistor 105. To avoid this, the countermeasure is taken such that the source of the transistor 105 is connected to the countermeasure voltage line xe2x80x9cViizxe2x80x9d and the drain of the transistor 106 is connected to the normal voltage line xe2x80x9cVssxe2x80x9d. During the standby mode, the switching device 101 is set in OFF state, the source of the transistor 105 is disconnected from the normal voltage line xe2x80x9cViixe2x80x9d due to the OFF state of the switching device 101, and the sub-threshold leaking current which tends to flow through the source/drain path of the transistor 105 is avoided by the connection of the source of the transistor 105 and the countermeasure voltage line xe2x80x9cViizxe2x80x9d.
In the above-described circuit of FIG. 1, the two-stage concatenated inverters are provided in the target circuit 107. Alternatively, multi-stage concatenated inverters may be provided in the target circuit 107. In such alternative case, the countermeasure against the sub-threshold leaking current is taken in the same manner. Namely, the source or drain of the transistor in each of the multi-stage concatenated inverters, which transistor is set in OFF state in the standby mode, is connected to the countermeasure voltage line xe2x80x9cViizxe2x80x9d or xe2x80x9cVssxxe2x80x9d in an alternate manner that is similar to the manner shown in FIG. 1.
FIG. 2 shows a sense buffer circuit in which the conventional method in FIG. 1 is incorporated. In the example of FIG. 2, the above-described conventional method to reduce the sub-threshold leaking current is applied to a sense buffer circuit of a semiconductor memory, such as a DRAM (dynamic random access memory).
In FIG. 2, xe2x80x9crgdbxxe2x80x9d and xe2x80x9crgdbzxe2x80x9d indicate complementary data bus signals that correspond to information of a memory cell read by a sense amplifier. A differential amplification section of the sense buffer circuit in FIG. 2 is essentially the same as a conventional differential amplifier.
In the sense buffer circuit 80 of FIG. 2, any of the normal voltage lines xe2x80x9cViixe2x80x9d and xe2x80x9cVssxe2x80x9d and the countermeasure voltage lines xe2x80x9cViizxe2x80x9d and xe2x80x9cVsszxe2x80x9d is connected to each of the respective elements of the sense buffer circuit 80. The incorporation of the conventional method in FIG. 1 into the sense buffer circuit 80 is achieved by the connection of the voltage lines and the circuit elements shown in FIG. 2. Similar to the circuit in FIG. 1, when the sense buffer circuit 80 of FIG. 2 is set in the active mode, the voltage of the power-source line xe2x80x9cViizxe2x80x9d is the same as the voltage of the power-source line xe2x80x9cViixe2x80x9d. When the sense buffer circuit 80 of FIG. 2 is set in the standby mode, the voltage of the power-source line xe2x80x9cViizxe2x80x9d is set in a floating state.
The sense buffer circuit 80 includes a p-channel MOS transistor 81 at the node xe2x80x9cnlOxe2x80x9d, a p-channel MOS transistor 82 at the node xe2x80x9cn12xe2x80x9d, an inverter 91 including a p-channel MOS transistor 83 and an n-channel MOS transistor 84, an inverter 92 including a p-channel MOS transistor 85 and an n-channel MOS transistor 86, an inverter 93 including a p-channel MOS transistor 87 and an n-channel MOS transistor 88, a p-channel MOS transistor 13 at the node xe2x80x9cn13xe2x80x9d, and an n-channel MOS transistor 11 at the node xe2x80x9cn11xe2x80x9d. The p-channel transistor 13 and the n-channel transistor 11 form a CMOS driver that drives the output node of the sense buffer circuit 80.
In the sense buffer circuit 80 of FIG. 2, a sense buffer enable signal xe2x80x9csbezxe2x80x9d is input. The sense buffer enable signal xe2x80x9csbezxe2x80x9d indicates whether the sense buffer circuit 80 is requested to be set in the active mode or the standby mode. When the signal xe2x80x9csbezxe2x80x9d is set at the high level (xe2x80x9cHxe2x80x9d), the sense buffer circuit 80 is set in the active mode. During the active mode, the differential amplification section of the sense buffer circuit 80 amplifies the complementary data buffer signals xe2x80x9crgdbzxe2x80x9d and xe2x80x9crgdbzxe2x80x9d corresponding to the information of the memory cell read by the sense amplifier, and outputs one of the amplified data signals to the node xe2x80x9cn10xe2x80x9d and the other amplified data signal to the node xe2x80x9cn12xe2x80x9d, respectively. The sense buffer circuit 80 outputs a read-back data signal xe2x80x9crdbzxe2x80x9d to a following circuit (for example, a latch circuit 90 in FIG. 3), the signal xe2x80x9crdbzxe2x80x9d being set at the high level (xe2x80x9cHxe2x80x9d) or the low level (xe2x80x9cLxe2x80x9d) in accordance with the amplified data signals at the nodes xe2x80x9cn11xe2x80x9d and xe2x80x9cn13xe2x80x9d.
On the other hand, when the sense buffer enable signal xe2x80x9csbezxe2x80x9d is set at the low level (xe2x80x9cLxe2x80x9d), the sense buffer circuit 80 is set in the standby mode. Namely, the sense buffer circuit 80 at that time is inactive. During the standby mode of the sense buffer circuit 80, the transistor 81 at the node xe2x80x9cnlOxe2x80x9d and the transistor 82 at the node xe2x80x9cn12xe2x80x9d are set in ON state in response to the low-level state of the input signal xe2x80x9csbezxe2x80x9d. Both the level of the node xe2x80x9cn10xe2x80x9d and the level of the node xe2x80x9cn12xe2x80x9d are set at the high level. The level of the node xe2x80x9cn11xe2x80x9d is equal to the potential of the normal voltage line xe2x80x9cVssxe2x80x9d, and the level of the node xe2x80x9cn13xe2x80x9d is equal to the potential of the normal voltage line xe2x80x9cViixe2x80x9d. Both the transistor 11 and the transistor 13 are set in OFF state. In this condition, the p-channel MOS transistor 83, the p-channel MOS transistor 87 and the n-channel MOS transistor 86 are set in OFF state. During the standby mode, the sub-threshold leaking current may occur at the transistors 83, 86 and 87 in the sense buffer circuit 80. To avoid this, the countermeasure is taken such that one end of each of the inverters 91, 92 and 93 is connected to the countermeasure voltage line xe2x80x9cViizxe2x80x9d or xe2x80x9cVssxxe2x80x9d. Hence, the conventional method in FIG. 1 is incorporated into the sense buffer circuit 80.
However, the output node of the sense buffer circuit 80, where the signal xe2x80x9crdbzxe2x80x9d is output to a following circuit, is connected to a latch circuit 90 (which is shown in FIG. 3), for the purposes of prevention of pass-through current and accuracy of output timing. Because of the latch circuit 90, the level of the output node of the sense buffer circuit 80 during the standby mode is not uniquely determined, which will be described in detail in the following.
FIG. 3 shows a latch circuit to which the sense buffer circuit in FIG. 2 is connected. For the sake of simplicity of description, suppose that the latch circuit 90 in FIG. 3 is a single-stage latch circuit, and this latch circuit 90 receives the signal xe2x80x9crdbzxe2x80x9d from the output node of the sense buffer circuit 80 in FIG. 2.
As shown in FIG. 3, the latch circuit 90 is constructed by two inverters that are concatenated: one of the inverters is formed by a pair of p-channel and n-channel MOS transistors 16 and 17, and the other inverter is formed by a pair of p-channel and n-channel MOS transistors 18 and 19. The latch circuit 90 serves to store a previous state of the output node of the sense buffer circuit 80 before it is set in the inactive condition (or before it is set in the standby mode).
FIG. 4 is a diagram for explaining operation of the sense buffer circuit 80 of FIG. 2 wherein the logic levels of the output node of the sense buffer circuit 80 are connected to the latch circuit 90 of FIG. 3.
As shown in FIG. 4, when the sense buffer enable signal xe2x80x9csbezxe2x80x9d is at the high level xe2x80x9cHxe2x80x9d, the sense buffer circuit 80 is set in the active mode. In this condition, the signal xe2x80x9crdbzxe2x80x9d, which is output by the sense buffer circuit 80, is set at the high level (xe2x80x9cHxe2x80x9d) or the low level (xe2x80x9cLxe2x80x9d) in accordance with the complementary data buffer signals xe2x80x9crgdbzxe2x80x9d and xe2x80x9crgdbzxe2x80x9d. When the signal xe2x80x9crdbzxe2x80x9d is at the high level, the transistor 11 and the transistor 13, which are provided at the output node of the sense buffer circuit 80, are set in OFF state and in ON state, respectively. The transistor 16 and the transistor 17 in the latch circuit 90 at that time are set in ON state and OFF state, and the transistor 18 and the transistor 19 are set in OFF state and ON state, respectively. Namely, the state of the output node of the sense buffer circuit 80 (the transistor 11 OFF and the transistor 13 ON) at that time is retained by the latch circuit 90.
Moreover, as shown in FIG. 4, when the signal xe2x80x9crdbzxe2x80x9d is at the low level during the active mode of the sense buffer circuit 80, the transistor 11 and the transistor 13 at the output node of the sense buffer circuit 80 are set in ON state and in OFF state, respectively. The transistor 16 and the transistor 17 in the latch circuit 90 at that time are set in OFF state and ON state, and the transistor 18 and the transistor 19 are set in ON state and OFF state, respectively. Namely, the state of the output node of the sense buffer circuit 80 (the transistor 11 ON and the transistor 13 OFF) at that time is retained by the latch circuit 90.
As described above, the transistors of the latch circuit 90 store the state of the output node of the sense buffer circuit 80 at the time the sense buffer circuit 80 is set in the active mode.
However, when the sense buffer enable signal xe2x80x9csbezxe2x80x9d is at the low level xe2x80x9cLxe2x80x9d, the sense buffer circuit 80 is set in the standby mode. That is, the sense buffer circuit 80 is inactive. The level of the node xe2x80x9cn11xe2x80x9d of the sense buffer circuit 80 is equal to the potential of the normal voltage line xe2x80x9cVssxe2x80x9d, and the level of the node xe2x80x9cn13xe2x80x9d is equal to the potential of the normal voltage line xe2x80x9cViixe2x80x9d. Both the transistor 11 and the transistor 13 at the output node are set in OFF state. In this condition, the transistors of the latch circuit 90 store the previous state of the output node of the sense buffer circuit 80 prior to the time the sense buffer circuit 80 is set in the inactive (or standby) mode. For this reason, the level of the output node of the sense buffer circuit 80 during the standby mode is not uniquely determined, and it is difficult to reduce the sub-threshold leaking current by applying the conventional method in FIG. 1 to the sense buffer circuit 80.
More specifically, if the signal xe2x80x9crdbzxe2x80x9d from the output node of the sense buffer circuit 80 is at the high level, the sub-threshold leaking current from the n-channel MOS transistor 11 may flow through the latch circuit 90. If the signal xe2x80x9crdbzxe2x80x9d is at the low level, the sub-threshold leaking current from the p-channel MOS transistor 13 may flow through the latch circuit 90.
Further, if the signal xe2x80x9crdbzxe2x80x9d is at the high level, the sub-threshold leaking current may flow into the transistors 18 and 17 of the latch circuit 90. If the signal xe2x80x9crdbzxe2x80x9d is at the low level, the sub-threshold leaking current may flow into the transistors 19 and 16 of the latch circuit 90. In order to effectively apply the conventional method in FIG. 1 to the sense buffer circuit 80, it is necessary that the level of the output node (the signal xe2x80x9crdbzxe2x80x9d) of the sense buffer circuit 80 during the standby mode be uniquely determined. However, if the level of the output node during the standby mode is not uniquely determined, the conventional method in FIG. 1 is not easily applied to the sense buffer circuit 80 so as to reduce the sub-threshold leaking current, and it is difficult for the sense buffer circuit 80 to provide low standby power consumption.
An object of the present invention is to provide an improved semiconductor integrated circuit in which the above-described problems are eliminated.
Another object of the present invention is to provide a semiconductor integrated circuit which is configured to enable the reduction of the sub-threshold leaking current across a node of the circuit even when the level of the node during the standby mode is not uniquely determined.
The above-mentioned objects of the present invention are achieved by a semiconductor integrated circuit having an active mode and a standby mode, comprising: a node at which an internal circuit is connected to a latch circuit, the latch circuit storing a data signal output from the internal circuit; and a level determination unit which determines a logic level of the node in response to a control signal indicating the standby mode.
The above-mentioned objects of the present invention are achieved by a semiconductor integrated circuit having an active mode and a standby mode, comprising: a node which is set at a logic level that is not uniquely determined in the standby mode; a pair of first transistors each of which has an output connected to the node, the first transistors driving the node to output a signal; a logic circuit which receives the signal from the node as an input signal and outputs a control signal based on the logic level of the node in the standby mode; and a pair of second transistors each of which is connected in series to one of the first transistors and being set in one of ON state and OFF state based on the control signal output by the logic circuit in the standby mode.
The above-mentioned objects of the present invention are achieved by a semiconductor integrated circuit having an active mode and a standby mode, comprising: a node which is set at a logic level that is not uniquely determined in the standby mode; and a CMOS driver which includes a p-channel transistor and an n-channel transistor each having an output connected to the node, the CMOS driver driving the node so as to output a data signal in the active mode, and the p-channel transistor and the n-channel transistor of the CMOS driver being set in OFF state in the standby mode, wherein the p-channel transistor and the n-channel transistor of the CMOS driver are connected to power-source voltage lines having a floating state in the standby mode.
According to the semiconductor integrated circuit of the present invention, it is possible to easily take the countermeasures against the sub-threshold leaking current by determining uniquely the level of the node of the circuit during the standby mode. In the semiconductor integrated circuit of the present invention the sub-threshold leaking current across the node of the circuit during the standby mode can be effectively reduced, and the semiconductor integrated circuit of the present invention is effective in reducing the standby power consumption.